发明名称 |
Strained InGaAs quantum wells for complementary transistors |
摘要 |
An InGaAs n-channel quantum well heterostructure for use in a complementary transistor having a Sb-based p-channel. The heterostructure includes a buffer layer having a lattice constant intermediate that of the n- and p-channel materials and which is configured to accommodate the strain produced by a lattice-constant mismatch between the n-channel and p-channel materials. |
申请公布号 |
US9054169(B2) |
申请公布日期 |
2015.06.09 |
申请号 |
US201414504559 |
申请日期 |
2014.10.02 |
申请人 |
The United States of America, as represented by the Secretary of the Navy |
发明人 |
Bennett Brian R.;Boos John Bradley;Chick Theresa F.;Champlain James G. |
分类号 |
H01L29/778;H01L29/15;H01L31/0352;H01L29/36;H01L29/66;H01L29/10;B82Y10/00;H01L27/092;H01L29/20 |
主分类号 |
H01L29/778 |
代理机构 |
US Naval Research Laboratory |
代理人 |
US Naval Research Laboratory ;Barritt Joslyn |
主权项 |
1. An InGaAs n-channel quantum well heterostructure, comprising:
a substrate; a first buffer layer disposed on the substrate, the first buffer layer being lattice-matched to the substrate; a second buffer layer disposed on the first buffer layer; a barrier layer disposed on the second buffer layer an InxGa1−xAs, x=0.53 to 1, n-channel layer disposed on the second buffer layer, the InxGa1−xAs n-channel material having a first lattice constant; a barrier layer disposed on the n-channel layer; a spacer layer disposed on the barrier layer; and a second barrier layer disposed on the spacer layer; wherein the heterostructure is configured for use with an antimonide-based p-channel layer in a complementary transistor, the p-channel layer having a second lattice constant different from the first lattice constant, a difference between the first and second lattice constants producing a strain between the n-channel layer and the p-channel layer in the complementary transistor; wherein the second buffer layer serves as a buffer layer for both the n-channel layer and the p-channel layer in the complementary transistor; and wherein the second buffer layer is configured to have a third lattice constant intermediate the first and second lattice constants and is configured to accommodate the strain produced by a lattice-constant mismatch between the n-channel layer and the p-channel layer in the complementary transistor. |
地址 |
Washington DC US |