High electron mobility transistor structure and method

摘要

Embodiments of the present disclosure describe structural configurations of an integrated circuit (IC) device such as a high electron mobility transistor (HEMT) switch device and method of fabrication. The IC device includes a buffer layer formed on a substrate, a channel layer formed on the buffer layer to provide a pathway for current flow in a transistor device, a spacer layer formed on the channel layer, a barrier layer formed on the spacer layer, the barrier layer including aluminum (Al), nitrogen (N), and at least one of indium (In) or gallium (Ga), a gate dielectric directly coupled with the spacer layer or the channel layer, and a gate formed on the gate dielectric, the gate being directly coupled with the gate dielectric. Other embodiments may also be described and/or claimed.

主权项

1. An apparatus comprising:
a buffer layer formed on a substrate, the buffer layer being epitaxially coupled with the substrate; a channel layer formed on the buffer layer to provide a pathway for current flow in a transistor device, the channel layer being epitaxially coupled with the buffer layer, wherein at least a portion of the channel layer is recessed; a spacer layer formed on the channel layer, the spacer layer being epitaxially coupled with the channel layer; a barrier layer formed on the spacer layer, the barrier layer being epitaxially coupled with the spacer layer, the barrier layer including aluminum (Al), nitrogen (N), and at least one of indium (In) or gallium (Ga); a gate dielectric directly coupled with the channel layer and formed within the recessed portion of the channel layer, wherein the gate dielectric includes a gate dielectric to surface and the channel layer includes a channel layer to surface, and wherein the channel layer to surface is lower than the gate dielectric to surface; and a gate electrode formed on the gate dielectric, the gate electrode being directly coupled with the gate dielectric, wherein each of the barrier layer, the spacer layer and the channel layer include first and second vertical sidewall surfaces, and wherein the gate electrode is in contact with the first and second vertical sidewall surfaces of the barrier layer, the spacer layer and the channel layer.