发明名称 Single event upset enhanced architecture
摘要 A circuit block within an integrated circuit includes a multiplexor (225, 625) configured to pass either a first signal or a second signal, wherein the first signal is independent of the second signal. The circuit block further includes a first flip-flop (210, 610) configured to receive an output of the multiplexor and a second flip-flop (215, 615) configured to receive the second signal. In a first mode of operation, the multiplexor passes the first signal to the first flip-flop. Further, the first flip flop and the second flip-flop operate independently of one another. In a second mode of operation, the multiplexor passes the second signal to the first flip-flop. Further, the first flip-flop and the second flip-flop both receive the second signal.
申请公布号 US9054684(B1) 申请公布日期 2015.06.09
申请号 US201313848689 申请日期 2013.03.21
申请人 XILINX, INC. 发明人 Sood Santosh Kumar;Jain Praful;Tanikella Ramakrishna K.
分类号 H03K5/125;G01R31/3181 主分类号 H03K5/125
代理机构 代理人 Cuenot Kevin T.
主权项 1. A circuit block within an integrated circuit, the circuit block comprising: a multiplexor configured to pass either a first signal or a second signal; wherein the first signal is independent of the second signal; a first flip-flop configured to receive an output of the multiplexor; wherein the first flip-flop has a first output and a second output; a second flip-flop comprising a first input configured to receive the second signal and a single event upset input coupled to a C-element block within the second flip-flop; wherein in a first mode of operation: the multiplexor passes the first signal to the first flip-flop; andthe first flip flop and the second flip-flop operate independently of one another with the second output of the first flip-flop gated so as to not transition; and wherein in a second mode of operation: the multiplexor passes the second signal to the first flip-flop;the first flip-flop and the second flip-flop both receive the second signal; anda first result signal generated by the second output of the first flip-flop is provided to the single event upset input of the second flip-flop bypassing a D-type element of the second flip-flop through which the second signal provided to the first input of the second flip-flop is processed.
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