Compact charge trap multi-time programmable memory

摘要

A method for enabling fabrication of memory devices requiring no or minimal additional mask for fabrication having a low cost, a small footprint, and multiple-time programming capability is disclosed. Embodiments include: forming a gate stack on a substrate; forming a source extension region in the substrate on one side of the gate stack, wherein no drain extension region is formed on the other side of the gate stack; forming a tunnel oxide liner on side surfaces of the gate stack and on the substrate on each side of the gate stack; forming a charge-trapping spacer on each tunnel oxide liner; and forming a source in the substrate on the one side of the gate stack and a drain in the substrate on the other side of the gate stack.

主权项

1. A method comprising:
forming a gate stack on a substrate; forming a source extension region in the substrate on one side of the gate stack, wherein no drain extension region is formed on the other side of the gate stack; forming a tunnel oxide liner on side surfaces of the gate stack and on the substrate on each side of the gate stack; forming a charge-trapping (CT) spacer on each tunnel oxide liner; and forming a source in the substrate on the one side of the gate stack and a drain in the substrate on the other side of the gate stack, wherein the source extension region and source are formed on the one side of the gate stack and the drain is formed on the other side of the gate stack with no drain extension region being formed.