Systems and methods for digital calibration of successive-approximation-register analog-to-digital converter

摘要

Systems and methods of calibrating a successive approximation register analog-to-digital converter (ADC) are disclosed. A plurality of capacitor stages, a first capacitor array, and a first capacitor stage are coupled in parallel. A capacitance of the first capacitor stage is compared to a sum of capacitances of the plurality of capacitor stages and of the first capacitor array. In response to the comparing, the capacitance of the first capacitor stage is increased by increasing the capacitance of a second capacitor array if the capacitance of the first capacitor stage is less than the sum of the capacitances of the plurality of capacitor stages and of the first capacitor array.

主权项

1. A method of calibrating an analog-to-digital converter (ADC), the method comprising:
comparing a capacitance of a first capacitor stage to a sum of capacitances of a plurality of capacitor stages and of a first capacitor array; and in response to the comparing, increasing the capacitance of the first capacitor stage by increasing the capacitance of a second capacitor array.