Fast exit from DRAM self-refresh

摘要

Embodiments of the invention describe a dynamic random access memory (DRAM) device that may abort a self-refresh mode to improve the exit time from a DRAM low power state of self-refresh. During execution of a self-refresh mode, the DRAM device may receive a signal (e.g., a device enable signal) from a memory controller operatively coupled to the DRAM device. The DRAM device may abort the self-refresh mode in response to receiving the signal from the memory controller.

主权项

1. A system comprising:
a synchronous dynamic random access memory (SDRAM) device comprising at least
a memory array,a mode register to hold at least one mode register bit, the value of the at least one mode register bit to determine whether a self-refresh abort mode is enabled, andcontrol logic coupled with the memory array, the control logic to abort a self-refresh in response, at least in part, to a self-refresh exit (SRX) command if the self-refresh abort mode is enabled, and otherwise to continue with the self-refresh in response to the SRX command; and a memory controller coupled with the SDRAM device, the memory controller including command and control logic to issue a valid command subsequent to the SRX command, wherein the timing of the valid command is tXS, if the self-refresh abort mode is not enabled and is less than tXS, if the self-refresh abort mode is enabled, where tXS is a time required to allow the SDRAM device to complete a self-refresh operation.