| 摘要 |
<p>Memory circuitry (2) includes an array (4) of bit cells (6). One or more boost capacitors C1 and C2 are connected to bit lines (8) running through the array (4) and serve to store a sample charge with a sample voltage difference during a sampling configuration of the boost capacitors C1, and C2. A boost configuration is subsequently adopted in which the boost capacitors C1 and C2 are connected with a different plurality to respective bit lines (8) such that the sample voltage difference is added to the voltage change within the bit line produced by the bit line cell (6) so as to generate an increased magnitude change in voltage which is supplied to sense amplifier circuitry (12).</p> |
