| 发明名称 |
PARALLEL DIGITAL-TO-TIME CONVERTER ARCHITECTURE |
| 摘要 |
This document discusses, among other things, digital-to-time converters (DTCs) and more particularly to parallel implementations of DTCs. In an example, an apparatus can include a first digital-to-time converter (DTC) configured to receive reference frequency information and first phase information of a polar transmitter and to provide a first portion of phase modulation information, a second DTC configured to receive second phase information of the polar transmitter and to provide a second portion of phase modulation information, and a combiner configured to receive the first portion and the second portion and to provide a phase modulated signal. |
| 申请公布号 |
US2015156044(A1) |
申请公布日期 |
2015.06.04 |
| 申请号 |
US201314096464 |
申请日期 |
2013.12.04 |
| 申请人 |
Madoglio Paolo;Pellerano Stefano |
发明人 |
Madoglio Paolo;Pellerano Stefano |
| 分类号 |
H04L27/20;H04L27/22;H03M1/68;H03M1/82;H03M1/74 |
主分类号 |
H04L27/20 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An apparatus comprising:
a first digital-to-time converter (DTC) configured to receive reference frequency information and first phase information and to provide a first portion of phase modulation information; a second DTC configured to receive second phase information and to provide a second portion of phase modulation information; and a combiner configured to receive the first portion and the second portion and to provide a phase modulated signal. |
| 地址 |
Beaverton OR US |
