Structure and Method For Statice Random Access Memory Device of Vertical Tunneling Field Effect Transistor

摘要

Forming an SRAM cell that includes first and second inverters cross-coupled for data storage, each inverter including at least one pull-up device and at least one pull-down devices; and at least two pass-gate devices configured with the two cross-coupled inverters, the pull-up devices, the pull-down devices and the pass-gate devices include a tunnel field effect transistor (TFET) that further includes a semiconductor mesa formed on a semiconductor substrate and having a bottom portion, a middle portion and a top portion; a drain of a first conductivity type formed in the bottom portion and extended into the semiconductor substrate; a source of a second conductivity type formed in the top portion, the second conductivity type being opposite to the first conductivity type; a channel in a middle portion and interposed between the source and drain; and a gate formed on sidewall of the semiconductor mesa and contacting the channel.

主权项

1. A method for fabricating a static random access memory (SRAM) cell, the method comprising:
forming a first inverter and second inverter, the first inverter and the second invertor being cross-coupled for data storage, each inverter including at least one pull-up (PU) device and at least one pull-down (PD) device; and forming at least two pass-gate (PG) devices configured with the first inverter and the second inverter, wherein the pull-up devices, the pull-down devices and the pass-gate devices each include a tunnel field effect transistor (TFET) that further includes:
a semiconductor mesa formed on a semiconductor substrate and having a bottom portion, a middle portion and a top portion;a drain of a first conductivity type formed in the bottom portion of the semiconductor mesa and extended into the semiconductor substrate;a source of a second conductivity type formed in the top portion of the semiconductor mesa, the second conductivity type being opposite to the first conductivity type;a channel in a middle portion of the semiconductor mesa and interposed between the source and drain; anda gate formed on sidewall of the semiconductor mesa and contacting the channel.