发明名称 |
ACTIVE LINEAR AMPLIFIER INSIDE TRANSMITTER MODULE |
摘要 |
In one example embodiment, a transmitter module includes a header electrically coupled to a chassis ground. First and second input nodes are configured to receive a differential data signal. A buffer stage has a first node coupled to the first input node and a second node coupled to the second input node. An amplifier stage has a fifth node coupled to a third node of the buffer stage and a sixth node coupled to a signal ground that is not coupled to the chassis ground. An optical transmitter has an eighth node coupled to a seventh node of the amplifier stage and a ninth node configured to be coupled to a voltage source. A bias circuit is configured to couple a fourth node of the buffer stage to a bias current source. |
申请公布号 |
US2015155949(A1) |
申请公布日期 |
2015.06.04 |
申请号 |
US201514612035 |
申请日期 |
2015.02.02 |
申请人 |
FINISAR CORPORATION |
发明人 |
Nguyen The'Linh;Daghighian Henry M. |
分类号 |
H04B10/564;H04B10/2575;H04B10/25 |
主分类号 |
H04B10/564 |
代理机构 |
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代理人 |
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主权项 |
1. A transmitter module with an active linear amplifier circuit, comprising:
a header electrically coupled to a chassis ground; a first input node configured to receive a first data signal; a second input node configured to receive a second data signal that is complementary of the first data signal; a buffer stage having a first node coupled to the first input node and a second node coupled to the second input node, wherein the first node is at a first base terminal of a first transistor and the second node is at a second base terminal of a second transistor; an amplifier stage having a fifth node coupled to a third node of the buffer stage and having a sixth node configured to be coupled to a signal ground, wherein the signal ground is not coupled to the chassis ground; an optical transmitter having an eighth node coupled to a seventh node of the amplifier stage and having a ninth node configured to be coupled to a voltage source; and a bias circuit configured to couple a fourth node of the buffer stage to a bias current source, wherein the fourth node is at a first collector terminal side of the first transistor and at a second collector terminal side of the second transistor. |
地址 |
Sunnyvale CA US |