| 摘要 |
An array substrate comprises data lines (405) configured on a substrate; a gate line group (401, 402) and a shared electrode line (403), which are mutually interleaved in two adjacent data lines (405) to define a pixel structure (400), wherein the pixel structure (400) comprises: a thin film transistor component (406); a first pixel electrode (410) and a second pixel electrode (411), which are configured between the gate line group (401, 402) and the shared electrode line (403); and a sharing capacitor (407), which is configured between the gate line group (401, 402) and the pixel electrodes (410, 411). The pixel structures (400) are arranged in multiple columns in an extension direction of the data lines (405). The pixel structures (400) in two adjacent columns are arranged sequentially in opposite directions, wherein charging gate lines (401) of the pixel structures (400) for which the gate line groups (401, 402) are close to each other in the two adjacent columns are juxtaposed together and centralized at a pixel boundary position, and use a position configuration of the sharing capacitor (407) to make a pixel opening area far away from light leakage areas (524, 534). Without a need of increasing a width of a black matrix (701), defects of a movable moire phenomenon and a low opening rate in prior art are solved. |
