发明名称 THRESHOLD VOLTAGE ADJUSTMENT IN METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR WITH SILICON OXYNITRIDE POLYSILICON GATE STACK ON FULLY DEPLETED SILICON-ON-INSULATOR
摘要 A fully depleted silicon-on-insulator MOSFET transistor with reduced variation in threshold voltage. The substrate of the transistor is doped to form a ground plane below a buried oxide layer. A lightly doped channel is formed over the buried oxide layer. A gate dielectric of Silicon Oxynitride is formed over the channel, and a polysilicon gate is formed over the gate dielectric. The polysilicon gate is doped to have a work function not greater 4.2 electron volts for a p-type doped channel (for an n-channel MOSFET), and not less than 5.0 electron volts for an n-type doped channel (for a p-channel MOSFET). The thickness of the buried oxide layer and the channel need not be greater than 20 nanometers and 10 nanometers, respectively.
申请公布号 US2015155364(A1) 申请公布日期 2015.06.04
申请号 US201314093105 申请日期 2013.11.29
申请人 QUALCOMM Incorporated 发明人 SONG Stanley Seungchul;YEAP Choh Fei
分类号 H01L29/49;H01L29/66;H01L29/51;H01L29/78 主分类号 H01L29/49
代理机构 代理人
主权项 1. An apparatus comprising: a silicon substrate; a doped ground plane formed in the silicon substrate; a buried oxide layer formed in the silicon substrate; a silicon channel formed on the buried oxide layer, the silicon channel doped p-type; a first source/drain region formed in the silicon channel; a second source/drain region formed in the silicon channel; a dielectric formed on the silicon channel; and a polysilicon gate formed on the dielectric, wherein the polysilicon gate has a work function not greater than 4.2 eV.
地址 San Diego CA US