Memory System Controller Including a Multi-Resolution Internal Cache

摘要

A memory system comprising a non-volatile memory and a controller in communication with the non-volatile memory is disclosed. The controller may include a central processing unit (“CPU”) and an internal cache in communication with the CPU via a plurality of cache lines. The CPU is configured to utilize a first subset of the plurality of cache lines when accessing data stored in the internal cache at a first resolution. Additionally, the CPU is configured to utilize a second subset of the plurality of cache lines when accessing data stored in the internal case at a second resolution, where the first and second resolutions are different resolutions.

主权项

1. A memory system comprising:
non-volatile memory; and a controller in communication with the non-volatile memory, the controller comprising:
a central processing unit; andan internal cache in communication with the central processing unit via a plurality of cache lines;wherein the central processing unit is configured to utilize a first subset of the plurality of cache lines when accessing data that is stored in the internal cache at a first resolution;wherein the central processing unit is configured to utilize a second subset of the plurality of cache lines when accessing data that is stored in the internal cache at a second resolution; andwherein the first resolution and the second resolution are different resolutions.