WARPAGE REDUCTION IN STRUCTURES WITH ELECTIRCAL CIRCUITRY

摘要

To reduce warpage in at least one area of a wafer, a stress/warpage management layer (810) is formed to over-balance and change the direction of the existing warpage. For example, if the middle of the area was bulging up relative to the area's boundary, the middle of the area may become bulging downward, or vice versa. Then the stress/warpage management layer is processed to reduce the over-balancing. For example, the stress/management layer can be debonded from the wafer at selected locations, or recesses can be formed in the layer, or phase changes can be induced in the layer. In other embodiments, this layer is tantalum-aluminum that may or may not over-balance the warpage; this layer is believed to reduce warpage due to crystal-phase-dependent stresses which dynamically adjust to temperature changes so as to reduce the warpage (possibly keeping the wafer flat through thermal cycling). Other features are also provided.

主权项

1. A manufacturing method comprising:
obtaining a first structure comprising electrical circuitry, the first structure comprising a first surface and a second surface opposite to the first surface, at least one of the first and second surfaces comprising a first area which is warped; forming a first layer on the first surface to over-balance a warpage of the first area; and processing the first layer to reduce the first area's warpage.