Methods for Layout Verification for Polysilicon Cell Edge Structures in FinFET Standard Cells using Filters

摘要

Methods for verifying the layout for standard cells using finFET standard cell structures with polysilicon on cell edges. Standard cells are defined using finFET transistors. Polysilicon dummy structures are formed on the edges of the active areas of the standard cells. Where two standard cells abut a single polysilicon dummy structure is formed. In a design flow, a pre-layout netlist schematic for the standard cells is formed that does not include devices corresponding to the polysilicon dummy structures. After an automated place and route process forms a device layout using the standard cells, a post layout netlist schematic is extracted including MOS devices corresponding to the polysilicon dummy structures. A layout versus schematic comparison is then performed, but during the comparison MOS devices corresponding to the polysilicon dummy structures are filtered from the post-layout netlist and are not compared. Additional methods are disclosed.

主权项

1. A method, comprising:
defining standard cells including at least one transistor and polysilicon dummy structures formed on cell edges; forming a pre-layout netlist schematic from an input gate level netlist using the standard cells, wherein the pre-layout netlist schematic does not include the polysilicon dummy structures; using the gate level netlist, performing an automated place and route process to form a layout netlist for fabricating an integrated circuit using the standard cells; laying out the standard cells and laying out routing connections between the standard cells to form a layout for the integrated circuit, using the layout netlist; extracting from the layout for the integrated circuit a post-layout netlist schematic, the post-layout netlist schematic including a MOS device for each polysilicon dummy structure of a standard cell in the layout netlist; and while using a filter to block the MOS devices corresponding to the polysilicon dummy structures from the post-layout netlist schematic, comparing the pre-layout netlist schematic to the post-layout netlist schematic.