CONTENTION MANAGEMENT FOR A HARDWARE TRANSACTIONAL MEMORY

摘要

A hardware transactional memory is provided within a multiprocessor system with coherency control and hardware transaction memory control circuitry that serves to at least partially manage the scheduling of processing transactions in dependence upon conflict data. The conflict data characterizes previously encountered conflicts between processing transactions. The scheduling is performed such that a candidate processing transaction will not be scheduled if the conflict data indicates that one of the already running processing transactions has previously conflicted with the candidate processing transaction.

主权项

1. A method of processing data using a plurality of processors and a transactional memory, said method comprising the steps of:
detecting with said transactional memory conflict arising between concurrent processing transactions executed by respective processors accessing shared data within said transactional memory; in response to said conflicts, storing conflict data for respective processing transactions indicative of with which other processing transactions a conflict has previously been detected; and scheduling processing transactions to be executed in dependence upon said conflict data.