SYSTEMS AND METHODS FOR SPECIFYING. MODELING, IMPLEMENTING AND VERIFYING IC DESIGN PROTOCOLS

摘要

A new approach is proposed that contemplates systems and methods to support a hybrid verification framework (HVF) to design, verify, and implement design protocols for an integrated circuit (IC) chip such as a system-on-chip (SOC) and/or an application-specific integrated circuit (ASIC) chip. The framework creates a plurality of specifications in form of extended state transition tables for different phases of a design flow of the IC chip. The framework integrates and uses the extended state table-based specifications and the templates in all phases in the design flow, resulting in a tight revision loop of debug, verification, and validation across the phases of the design flow.

主权项

1. 1. A system, comprising:
a formal verification engine running on a host, which in operation, automatically generates and formally verifies a reference specification that includes a plurality of extended state tables for an integrated circuit (IC) design protocol of a chip at architectural level; a protocol checking engine running on a host, which in operation, checks and validates completeness and correctness of the reference specification; a micro architect engine running on a host, which in operation, implements the IC design protocol at the micro-architectural level using a synthesizable package generated from the formally verified reference specification; a dynamic verification (DV) engine running on a host, which in operation, dynamically verifies the implementation of the IC design protocol at the micro-architectural level and incorporates all incremental changes to the IC design protocol in real time based on a DV reference model generated from the extended state tables of the reference specification.