| 发明名称 |
ESTIMATING DELAY DETERIORATION DUE TO DEVICE DEGRADATION IN INTEGRATED CIRCUITS |
| 摘要 |
A system for estimating delay deterioration in an integrated circuit includes a degradation estimator for estimating degradation for each of one or more lifetimes in at least one characteristic of each device defined within the integrated circuit using voltages and logic values monitored during a simulation of the integrated circuit. A netlist generator generates an end-of-life netlist for each of the one or more lifetimes in which the at least one device characteristic of each device has been modified to reflect each of the estimated degradations. A timing analyzer performs a timing analysis on each of the end-of-life netlists to determine static or statistical circuit path delays over the one or more lifetimes. |
| 申请公布号 |
US2015154331(A1) |
申请公布日期 |
2015.06.04 |
| 申请号 |
US201514616135 |
申请日期 |
2015.02.06 |
| 申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
Bansal Aditya;Kim Jae-Joon;Rao Rahul M. |
| 分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A system for estimating delay deterioration in an integrated circuit comprising:
a degradation estimator for estimating degradation for each of one or more lifetimes in at least one characteristic of each device defined within the integrated circuit using voltages and logic values monitored during a simulation of the integrated circuit; a netlist generator for generating an end-of-life netlist for each of the one or more lifetimes in which the at least one device characteristic of each device has been modified to reflect each of the estimated degradations; and a timing analyzer for performing a timing analysis on each of the end-of-life netlists to determine static or statistical circuit path delays over the one or more lifetimes. |
| 地址 |
Armonk NY US |
