发明名称 |
SEMICONDUCTOR INTEGRATED CIRCUIT |
摘要 |
An input buffer chooses, in accordance with first control clocks, to output an input data signal or output a high-impedance signal. A master flip-flop chooses, in accordance with second control clocks, to output a data signal received from the input buffer or retain a currently output data signal. A master-slave switch chooses, in accordance with the second control clocks, to output a high-impedance signal or output a data signal received from the master flip-flop. A slave flip-flop chooses, in accordance with the second control clocks, to retain a currently output data signal or output a data signal received from the master-slave switch. A clock buffer inputs the second control clocks, and generates and outputs the first control clocks. |
申请公布号 |
US2015154924(A1) |
申请公布日期 |
2015.06.04 |
申请号 |
US201514617160 |
申请日期 |
2015.02.09 |
申请人 |
RENESAS ELECTRONICS CORPORATION |
发明人 |
YOKOYAMA Masanao;OKUZONO Noboru |
分类号 |
G09G3/36 |
主分类号 |
G09G3/36 |
代理机构 |
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代理人 |
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主权项 |
1. A semiconductor integrated circuit configured to drive a liquid crystal display (LCD), comprising:
an input buffer configured to choose, in accordance with a first control clock, to output an input data signal or output a high-impedance signal; a master flip-flop configured to choose, in accordance with a second control clock, to output a data signal received from the input buffer or retain a currently output data signal; a master-slave switch configured to choose, in accordance with the second control clock, to output a high-impedance signal or output a data signal received from the master flip-flop; a slave flip-flop that chooses, in accordance with the second control clock, to retain a currently output data signal or output a data signal received from the master-slave switch; a first clock buffer configured to receive an external clock and output the second control clock; and a second clock buffer configured to receive the second control clock, retard rising and/or falling edges of the second control clock, and output the first control clock, wherein the input buffer does not receive the second control clock, wherein each of the master flip-flop, master-slave switch, and slave flip-flop does not receive the first control clock. |
地址 |
Kanagawa JP |