| 发明名称 |
APPARATUS FOR TIME DOMAIN OFFSET CANCELLATION TO IMPROVE SENSING MARGIN OF RESISTIVE MEMORIES |
| 摘要 |
Described are apparatuses for time domain offset cancellation. One example of the apparatus includes: a variable resistance memory cell; a reference resistive memory cell; a detector to generate an output indicating timing relationship between a pulse arriving from the variable resistance memory cell and a pulse arriving from the reference resistive memory cell; and a logic unit to receive the output from the detector and to generate a control signal to the adjust timing relationship as indicated by the detector. |
| 申请公布号 |
US2015155036(A1) |
申请公布日期 |
2015.06.04 |
| 申请号 |
US201314094488 |
申请日期 |
2013.12.02 |
| 申请人 |
AUGUST Nathaniel J.;WEI Liqiong |
发明人 |
AUGUST Nathaniel J.;WEI Liqiong |
| 分类号 |
G11C13/00 |
主分类号 |
G11C13/00 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An apparatus comprising:
a variable resistance memory cell; a reference resistive memory cell; a detector to generate an output indicating timing relationship between a pulse arriving from the variable resistance memory cell and a pulse arriving from the reference resistive memory cell; and a logic unit to receive the output from the detector and to generate a control signal to the adjust timing relationship as indicated by the detector. |
| 地址 |
Portland OR US |
