| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To impose appropriate timing constraints, independently of a designer, on a design tool used in a downstream process that is performed after logic synthesis in design of a semiconductor integrated circuit. <P>SOLUTION: A semiconductor design support device is provided with: means for performing clarification processing of all clocks included in a source code from a result of a CDC verification which is performed for the source code in design of an electric circuit containing an asynchronous circuit and from known information which is defined in a specification development process and used for coding the source code, and collectively obtaining a CDC verification setting file; and means for extracting, from the CDC verification setting file and an input/output path for each asynchronous path which is obtained from the CDC verification result, predetermined information in accordance with a format readable by a design tool used in a downstream process, and generating and outputting a timing constraint file. <P>COPYRIGHT: (C)2012,JPO&INPIT</p> |
