发明名称 |
Instruction set for message scheduling of SHA256 algorithm |
摘要 |
<p>A processor includes a first execution unit to receive and execute a first instruction to process a first part of secure hash algorithm 256 (SHA256) message scheduling operations, the first instruction having a first operand associated with a first storage location to store a first set of message inputs and a second operand associated with a second storage location to store a second set of message inputs. The processor further includes a second execution unit to receive and execute a second instruction to process a second part of the SHA256 message scheduling operations, the second instruction having a third operand associated with a third storage location to store an intermediate result of the first part and a third set of message inputs and a fourth operand associated with a fourth storage location to store a fourth set of message inputs.</p> |
申请公布号 |
GB2520858(A) |
申请公布日期 |
2015.06.03 |
申请号 |
GB20150000993 |
申请日期 |
2013.06.12 |
申请人 |
INTEL CORPORATION |
发明人 |
GILBERT M WOLRICH;KIRK S YAP;JAMES D GUILFORD;VINODH GOPAL;SEAN M GULLEY |
分类号 |
G06F9/46;G06F9/38;H04L9/00 |
主分类号 |
G06F9/46 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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