| 摘要 |
A vertical shift register section 40a, 40b includes M logic circuits LO 1 to LO M for outputting row selection control signals respectively to M row selection wiring lines L V,1 to L V,M and shift register circuits 43 disposed for every two row selection wiring lines L V . The M logic circuits LO 1 to LO M , when a binning control signal Vbin 1 or Vbin 2 and an output signal of the shift register circuit 43 both have significant values, output a row selection control signal Vsel so as to close a readout switch SW 1 . The vertical shift register section 40a, 40b, by controlling the timing at which the binning control signals Vbin 1 and Vbin 2 take significant values, realizes a normal operation mode for successively selecting the two row selection wiring lines L V and a binning operation mode for simultaneously selecting the two row selection wiring lines L V . Accordingly, a vertical binning operation is realized by a small vertical shift register. |
