Low-power encryption apparatus and method

摘要

A low-power encryption apparatus and method are provided. The low-power encryption apparatus includes a mask value generation unit, a mask value application unit, a round key application unit, a mask operation unit, a shift operation unit, and a shift operation correction unit. The mask value generation unit generates a mask value M having the same bit length as input round function values. The mask value application unit generates first masking round function values by applying the mask value M. The round key application unit generates second masking round function values by applying round key values. The mask operation unit generates third masking round function values by performing a mask addition operation. The shill operation unit generates fourth masking round function values by performing a circular shift operation. The shift operation correction unit generates output round function values by performing an operation using the mask value M.

主权项

1. A low-power plaintext encryption apparatus comprising:
a plaintext input chip configured to receive from a user a plaintext P which is a concatenation of a plurality of sub-plaintexts each having a same length of bits; a mask value generation chip configured to generate a mask value M having a bit length identical to that of input round function values generated from the plurality of sub-plaintexts received from the plaintext input chip; a mask value application chip configured to generate first masking round function values by applying the mask value M to each of the input round function values; a round key application chip configured to generate second masking round function values by applying round key values to the first round function values; a mask operation chip configured to generate third masking round function values by performing a mask addition operation on the second masking round function values; a shift operation chip configured to generate fourth masking round function values by performing a circular shift operation on the third masking round function values; a shift operation correction chip configured to generate output round function values by performing an operation using the mask value M on the fourth masking round function values, and a plaintext output chip configured to output an encrypted plaintext P′ having a same length of bits by concatenating the output round function values, wherein the input round function values are an input round function value Xi[0], an input round function value Xi[1], an input round function value Xi[2], and an input round function value Xi[3], wherein the mask value application chip: generates a first masking round function value Xi—1[0] from the input round function value Xi[0] and the mask value M based on an equation “Xi—1[0]=Xi[0]⊕M”; generates a first masking round function value Xi—1[1] from the input round function value Xi[1] and the mask value M based on an equation “Xi—1[1]=Xi[1]⊕M”; generates a first masking round function value Xi—1[2] from the input round function value Xi[2] and the mask value M based on an equation “Xi—1[2]=Xi[2]⊕M”; and generates a first masking round function value Xi—1[3] from the input round function value Xi[3] and the mask value M based on an equation “Xi—1[3]=Xi[3]⊕M”; wherein ⊕ is an exclusive OR (XOR) operator, and wherein the round key values are a round key value RKi[0], a round key value RKi[1], a round key value RKi[2], a round key value RKi[3], a round key value RKi[4], and a round key value RKi[5].