发明名称 |
Contact and via interconnects using metal around dielectric pillars |
摘要 |
An integrated circuit containing a vertical interconnect that includes a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure. An upper conductive structure contacts a top surface of the vertical interconnect. A process of forming an integrated circuit that includes forming a vertical interconnect that has a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure, and an upper conductive structure contacts a top surface of the vertical interconnect. |
申请公布号 |
US9048297(B2) |
申请公布日期 |
2015.06.02 |
申请号 |
US201314098255 |
申请日期 |
2013.12.05 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
Summerfelt Scott R. |
分类号 |
H01L21/332;H01L21/768;H01L23/522;H01L23/532;H01L23/528 |
主分类号 |
H01L21/332 |
代理机构 |
|
代理人 |
Keagy Rose Alyssa;Cimino Frank D. |
主权项 |
1. A process of forming an integrated circuit, comprising the steps of:
forming a lower conductive structure in a lower region; forming an interlevel dielectric layer on a top surface of said lower region forming a vertical interconnect by a process further including the steps of:
forming at least one dielectric pillar on a top surface of said lower conductive structure;forming a trench within said interlevel dielectric layer for an upper lateral interconnect;forming a region of interconnect metal, such that said interconnect metal continuously surrounds each said at least one dielectric pillar, every location in said interconnect metal region is within a desired maximum horizontal distance from a boundary of said interconnect metal, and said interconnect metal electrically contacts said lower conductive structure, said boundary includes edges of said interconnect metal region and perimeters of said pillars, wherein a bottom plane of said upper lateral interconnect trench and a top surface of each said at least one dielectric pillar are substantially coplanar; and forming an upper conductive structure within said upper lateral interconnect trench, said upper conductive structure contacting a top surface of said vertical interconnect. |
地址 |
Dallas TX US |