System and method for analog verification IP authoring and storage

摘要

A system, method, and computer program product for automatically providing circuit designers with verification information for analog and mixed-signal circuit designs. A graphical user interface based environment allows circuit designers to enter verification IP while simultaneously viewing the design IP in a schematic and/or layout editor window. Embodiments maintain the verification IP in a cellview similar to the separate cellviews used for schematic and layout data. Verification IP may be selectively translated into data that is directly exportable to and usable by particular analog and mixed-signal simulators. Embodiments direct design IP and verification IP to a simulator that dynamically stitches both together during circuit verification, and tangibly outputs verification results.

主权项

1. A computer-implemented method for managing circuit design verification IP, the method comprising:
creating verification IP that defines checks for verifying operation of a circuit design, using a dedicated verification IP user interface separate from a design IP user interface; storing the verification IP as a separate verification IP view for subsequent retrieval; using a computer and the verification IP, simulating the circuit design with a circuit simulator to generate circuit design verification results; and outputting the circuit design verification results.