Circuitry to facilitate testing of serial interfaces

摘要

Circuitry to facilitate testing of serial interfaces is described. Specifically, some embodiments of the present invention facilitate testing the clock and data recovery functionality of a receiver. A serial interface can include a multiplying phase locked loop (MPLL) clock generator, a transmitter, and a receiver. The MPLL clock generator can generate a first clock signal and a second clock signal, and can vary a phase and/or frequency difference between the first clock signal and the second clock signal. During test, the transmitter and the receiver can be directly or capacitively coupled to each another. Specifically, during test, the serial interface can be configured so that the transmitter transmits data using the first clock signal, and the receiver receives data using the second clock signal. The clock and data recovery functionality of the receiver can be tested by comparing the transmitted data with the received data.

主权项

1. A serial interface, comprising:
a multiplying phase locked loop (MPLL) clock generator to generate a first clock signal and a second clock signal, wherein the MPLL comprises a programmable phase mixer to vary the phase difference between the first clock signal and the second clock signal based on a control signal; a transmitter which, during test, transmits data using the first clock signal; a receiver which, during test, receives data using the second clock signal; wherein, during test, the data transmitted by the transmitter is looped back to the receiver; and wherein, during test, the control signal is used to vary the phase difference between the first clock signal and the second clock signal while the transmitter is transmitting data using the first clock signal and the receiver is receiving data using the second clock signal.