发明名称 Minimum mean square error processing
摘要 A first systolic array receives an input set of time division multiplexed matrices from a plurality of channel matrices. In a first mode, the first systolic array performs triangularization on the input matrices, producing a first set of matrices, and in a second mode performs back-substitution on the first set, producing a second set of matrices. In a first mode, a second systolic array performs left multiplication on the second set of matrices with the input set of matrices, producing a third set of matrices. In a second mode, the second systolic array performs cross diagonal transposition on the third set of matrices, producing a fourth set of matrices, and performs right multiplication on the second set of matrices with the fourth set of matrices. The first systolic array switches from the first mode to the second mode after the triangularization, and the second systolic array switches from the first mode to the second mode after the left multiplication.
申请公布号 US9047241(B2) 申请公布日期 2015.06.02
申请号 US201313751929 申请日期 2013.01.28
申请人 XILINX, INC. 发明人 Mazahreh Raied N.;Tarn Hai-Jo;Rao Raghavendar M.
分类号 G06F15/80;G06F17/16;G06F7/78;H04B7/04;H04B7/08;H04L25/02 主分类号 G06F15/80
代理机构 代理人 Maunu LeRoy D.
主权项 1. A systolic array for right multiplication, left multiplication, and cross diagonal transposition, comprising: a plurality of processing cells, including boundary cells and internal cells, and arranged into: N rows of processing cells, each row M beginning with a boundary cell and continuing with a number of internal cells equal to the number N minus M, wherein 1≦M≦N; andN columns of processing cells, each column L containing L minus one internal cells followed by one boundary cell, wherein 1≦L≦N; wherein: the systolic array is configurable to operate in a first mode and a second mode;while operating in the first mode, processing cells of the systolic array are configured and interconnected to receive first and second input matrices and perform left multiplication of the first input matrix with the second input matrix to produce a first output matrix;while operating in the second mode: processing cells of the systolic array are configured and interconnected to produce a cross diagonal transposition on the first output matrix; andperform right multiplication of the cross diagonal transposition of the first output matrix with the first input matrix to produce a second output matrix.
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