发明名称 Data transfer bus communication to receive data by sending request instruction attached with identifier indicating processor and thread context identities
摘要 Systems and methods for managing context switches among threads in a processing system. A processor may perform a context switch between threads using separate context registers. A context switch allows a processor to switch from processing a thread that is waiting for data to one that is ready for additional processing. The processor includes control registers with entries which may indicate that an associated context is waiting for data from an external source.
申请公布号 US9047093(B2) 申请公布日期 2015.06.02
申请号 US200912429655 申请日期 2009.04.24
申请人 ARM Finance Overseas Limited 发明人 Gelinas Robert;Hays W. Patrick;Katzman Sol;Dally William J.
分类号 G06F9/46;G06F9/312;G06F9/38;G06F9/30 主分类号 G06F9/46
代理机构 Patterson Thuente Pedersen, P.A. 代理人 Patterson Thuente Pedersen, P.A.
主权项 1. A processing system, comprising: a processor; and a controller coupled to the processor and configured to be coupled to a bus, to send an instruction to a device coupled to the bus, and to add a first identifier to the instruction to indicate an identity of the processor and an identity of a context of a thread that produced the instruction, wherein the device is configured and arranged to return data to the processor identified by the first identifier.
地址 Cambridge GB