Computer-aided design (CAD) multiple-capture DFT system for detecting or locating crossing clock-domain faults

摘要

A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.

主权项

1. A computer-aided design (CAD) method for generating a testable hardware description language (HDL) code or netlist to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test mode, where N>1, the integrated circuit or circuit assembly being represented by an HDL code or netlist, each clock domain having one or more capture clocks and one or more scan cells, each capture clock comprising a selected number of shift clock pulses and a selected number of capture clock pulses, each shift clock pulse comprising a clock pulse applied in scan mode, each capture clock pulse comprising a clock pulse applied in normal mode, said method comprising using a computer for: (a) compiling said HDL code or netlist that represents said integrated circuit or circuit assembly; (b) checking whether said HDL code or netlist complies with scan rules; (c) repairing violations of said scan rules in said HDL code or netlist; and (d) performing scan synthesis for generating said testable HDL code or netlist in accordance with a multiple-capture design-for-test (DFT) technique.