发明名称 Accessing additional memory space with multiple processors
摘要 An apparatus and method is provided for coupling additional memory to a plurality of processors. The method may include determining the memory requirements of the plurality of processors in a system, comparing the memory requirements of the plurality of processors to an available memory assigned to each of the plurality of processors, and selecting a processor from the plurality of processors that requires additional memory capacity. The apparatus may include a plurality of processors, where the plurality of processors is coupled to a logic element. In addition, the apparatus may include an additional memory coupled to the logic element, where the logic element is adapted to select a processor from the plurality of processors to couple with the additional memory.
申请公布号 US9047057(B2) 申请公布日期 2015.06.02
申请号 US201213679496 申请日期 2012.11.16
申请人 International Business Machines Corporation 发明人 Cordero Edgar R.;Haridass Anand;Vidyapoornachary Diyanesh B.;Tremaine Robert B.
分类号 G06F12/02;G06F3/16;G06F9/50 主分类号 G06F12/02
代理机构 代理人 Berger Scott A.;Williams Robert R.
主权项 1. A system for coupling additional memory to a plurality of processors, comprising: a switching device; a plurality of processors, the plurality of processors each coupled to the switching device; a plurality of memory modules coupled to the plurality of processors, wherein at least one memory module of the plurality of memory modules is coupled to a processor of the plurality of processors; additional memory that is distinct from the plurality of memory modules, the additional memory coupled to the switching device; and a controller, wherein the controller is adapted to signal the switching device to couple the additional memory to a processor from the plurality of processors, and wherein the controller uses parameters to determine a priority, in terms of duration, of an exclusive use of the additional memory by the processor from the plurality of processors.
地址 Armonk NY US