| 发明名称 | Semiconductor device having a high breakdown voltage | ||
| 摘要 | A semiconductor device includes a first layer of a first-type, a second layer of a second-type formed on the first layer, a third layer of the first type formed on the second layer, a first electrode connected to the second and third layers, a second electrode connected to the first layer, a third electrode embedded in a trench formed through the third and second layers and into the first layer, a fourth electrode embedded in the trench below the third electrode, and an insulating layer formed in the trench around the fourth electrode. The first layer includes a first region that is in contact with the insulating layer and at which a concentration of the first-type dopant is lower than the concentration at a second region that is formed around the first region. | ||
| 申请公布号 | US9048215(B2) | 申请公布日期 | 2015.06.02 |
| 申请号 | US201314014260 | 申请日期 | 2013.08.29 |
| 申请人 | Kabushiki Kaisha Toshiba | 发明人 | Asahara Hidetoshi |
| 分类号 | H01L29/78;H01L29/40;H03K17/041 | 主分类号 | H01L29/78 |
| 代理机构 | Patterson & Sheridan LLP | 代理人 | Patterson & Sheridan LLP |
| 主权项 | 1. A semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer; a third semiconductor layer of the first conductivity type provided on the second semiconductor layer; a first electrode electrically connected to the second semiconductor layer and the third semiconductor layer; a second electrode electrically connected to the first semiconductor layer; a third electrode embedded in a trench provided through the third semiconductor layer and the second semiconductor layer and into the first semiconductor layer; a fourth electrode embedded in the trench below the third electrode; and an insulating layer provided in the trench around the fourth electrode, wherein the first semiconductor layer includes a first region that is in contact with the insulating layer and at which a concentration of a first conductivity type dopant is lower than the concentration of the first conductivity type dopant at a second region of the first semiconductor layer that is provided around the first region and wherein a concentration of a second conductivity type dopant is uniform across the second semiconductor layer. | ||
| 地址 | Tokyo JP | ||