Apparatus and method for separate asymmetric control processing and data path processing in a dual path processor

摘要

According to embodiments of the invention, there is disclosed a computer processor architecture; and in particular a computer processor, a method of operating the same, and a computer program product that makes use of an instruction set for the computer. In one embodiment according to the invention, there is provided a computer processor, the processor comprising: a decode unit for decoding instruction packets fetched from a memory holding a sequence of instruction packets; and first and second processing channels, each channel comprising a plurality of functional units, wherein the first processing channel is capable of performing control operations and comprises a control register file having a relatively narrower bit width, and the second processing channel is capable of performing data processing operations at least one input of which is a vector and comprises a data register file having a relatively wider bit width. The decode unit is operable to detect for each instruction packet whether the instruction packet defines (i) a plurality of control instructions to be executed sequentially on the first processing channel or (ii) a plurality of instructions comprising at least one data processing instruction to be executed simultaneously on the second execution channel, and to control the first and second channels in dependence on said detection.

主权项

1. A computer processor for processing (i) instruction packets comprising a plurality of only control instructions, the control instructions having a control bit width, and (ii) instruction packets comprising a plurality of instructions comprising at least one data processing instruction, the data processing instructions having a data processing bit width wider than the control bit width, the processor comprising:
a decode unit for decoding sequentially the instruction packets fetched from a memory holding the instruction packets, the instruction packets being all of equal bit length; a control processing channel capable of performing control operations, the control processing channel comprising a plurality of functional units including a control register file having a first bit width; and a data processing channel capable of performing data processing operations at least one input of which is a vector, the data processing channel comprising a plurality of functional units including a data register file having a second bit width, wider than the first bit width; wherein the decode unit comprises decode circuitry configured to decode identification bits of each instruction packet to determine which type (i), (ii), of instruction packet is being decoded, and control circuitry configured to pass the plurality of only control instructions having the control bit width from an instruction packet of type (i) to the control processing channel when the decode circuitry indicates so and to pass the plurality of instructions comprising at least one data processing instruction having the data processing bit width wider than the control bit width from an instruction packet of type (ii) to the data processing channel when the decode circuitry indicates so; wherein, in use the decode unit causes instructions of (i) instruction packets comprising a plurality of only control instructions to be executed sequentially on the control processing channel; and wherein, in use the decode unit causes instructions of (ii) instruction packets comprising a plurality of instructions comprising at least one data processing instruction to be executed simultaneously on the data processing channel.