Compression of processor instructions

摘要

A custom processor is adapted for performing at least one predetermined application. The instruction sequence for the custom processor is compressed by performing at least one identification process on the instructions of the instruction sequence, in order to identify relationships between the contents of the bit positions in the instructions. A compressed instruction sequence then includes one compressed instruction corresponding to each instruction of the predetermined instruction sequence, with each compressed instruction comprising a reduced number of bits, based on the identified relationships between the contents of said bit positions in said instructions of said predetermined instruction sequence.

主权项

1. A processor for compressing an instruction sequence, wherein the instruction sequence includes a plurality of instructions, each instruction comprising a first number of bits in respective bit positions, the processor operating in accordance with:
commands to perform at least one identification process on the instruction sequence in order to identify relationships between the bits in said bit positions among the instructions of the instruction sequence, wherein the identification process identifies pairs of bit positions in the instructions of the instruction sequence which contain opposite bit values from each other; and commands to generate a compressed instruction sequence comprising one compressed instruction corresponding to each instruction of the instruction sequence based on the identification process.