Semiconductor memory card

摘要

According to one embodiment, a semiconductor memory card includes a first pin group which includes a plurality of pins arranged in a line at an end portion on a side of an inserting direction into a connector and part of which is used both in a first and second modes; and a second pin group which includes a plurality of pins including at least two pin pairs for differential signal, is arranged so that a ground is positioned on both sides of each of the pin pairs for differential signal, and is used only in the second mode. In the second mode, among the respective pins configuring the first pin group, any of adjacent two pins are changed to a pin pair for differential clock signal, and a function of remaining pins of the first pin group is stopped.

主权项

1. A semiconductor memory card that includes a semiconductor memory that is mounted on one surface of a substrate and a controller that is mounted on the other surface of the substrate and controls the semiconductor memory, and is capable of operating in a first mode and a second mode in which data is transferred at a higher speed than the first mode, comprising:
a first pin group which includes a plurality of pins arranged in a line at an end portion on a side of an inserting direction into a connector, which functions as four data pins, one command pin, one power source pin, one clock pin, and two ground pins in the first mode, and part of which is used both in the first and second modes; and a second pin group which includes a plurality of pins including at least two pin pairs for differential signal, is arranged so that a ground is positioned on both sides of each of the pin pairs for differential signal, and is used only in the second mode, wherein in the second mode, among the respective pins configuring the first pin group, any of adjacent two out of ones that function as the data pins, the command pin, and the clock pin in the first mode are changed to a pin pair for differential clock signal to function as the pin pair for differential clock signal, and a function of remaining pins of the first pin group is stopped.