发明名称 |
Light emitting diode package |
摘要 |
A light emitting diode package includes a package body having a cavity, a light emitting diode chip having a plurality of light emitting cells connected in series to one another, a phosphor converting a frequency of light emitted from the light emitting diode chip, and a pair of lead electrodes. The light emitting cells are connected in series between the pair of lead electrodes. |
申请公布号 |
US9048391(B2) |
申请公布日期 |
2015.06.02 |
申请号 |
US201414320380 |
申请日期 |
2014.06.30 |
申请人 |
Seoul Semiconductor Co., Ltd. |
发明人 |
Jung Jung Hwa;Oh Hee Tak;Kim Do Hyung;Kwon You Jin;Kim Oh Sug |
分类号 |
H01L33/00;H01L21/00;H01L33/48;H01L25/075;H01L33/62;H01L33/58;H01L25/16;H01L33/64 |
主分类号 |
H01L33/00 |
代理机构 |
H.C. Park & Associates, PLC |
代理人 |
H.C. Park & Associates, PLC |
主权项 |
1. A light emitting diode package comprising:
a package body comprising: a plurality of upper conductive patterns disposed on an upper surface of a dielectric substrate; a plurality of lower conductive patterns disposed on a lower surface of the dielectric substrate, the dielectric substrate having a cut plane portion perpendicular to the upper and lower surfaces of the dielectric substrate; conductive materials extending from the upper conductive patterns to the lower conductive patterns through an interior of the dielectric substrate; a first heat sink pattern disposed on the lower surface of the dielectric substrate and separated by a fixed distance from the upper conductive patterns; and a light emitting diode chip mounted on the package body; wherein an edge portion of at least one of an upper conductive pattern of the plurality of upper conductive patterns and a lower conductive pattern of the plurality of lower conductive patterns is not aligned in the same plane as the cut plane portion of the dielectric substrate. |
地址 |
Ansan-si KR |