Non-coherent store instruction for fast inter-strand data communication for processors with write-through L1 caches

摘要

A method is disclosed that uses a non-coherent store instruction to reduce inter-thread communication latency between threads sharing a level one write-through cache. When a thread executes the non-coherent store instruction, the level one cache is immediately updated with the data value. The data value is immediately available to another thread sharing the level-one write-through cache. A computer system having reduced inter-thread communication latency is disclosed. The computer system includes a first plurality of processor cores, each processor core including a second plurality of processing engines sharing a level one write-through cache. The level one caches are connected to a level two cache via a crossbar switch. The computer system further implements a non-coherent store instruction that updates a data value in the level one cache prior to updating the corresponding data value in the level two cache.

主权项

1. A method for reducing inter-thread communication latency in a multiprocessor system having a cache hierarchy with a write-through level one cache, the method comprising:
providing a non-coherent store instruction; scheduling a first thread on a first hardware context associated with the write-through level one cache; scheduling a second thread on a second hardware context sharing the write-through level one cache; within the first thread, executing the non-coherent store instruction to pass a data value from the first thread to the second thread; and updating the shared write-through level one cache prior to updating a cache level at which a cache coherency policy is enforced such that the data value is passed from the first thread to the second thread before the data value is updated in the cache level at which the cache coherency policy is enforced.