发明名称 |
Duty cycle compensation of RAM transmitters |
摘要 |
Disclosed embodiments may include a circuit having a clock-to-output (TCO) compensation circuit coupled to a RAM pull-up transmitter and a RAM pull-down transmitter. The TCO compensation circuit may be configured to compare a first output with a second output and to generate a delay code, based on the comparison, for at least one other RAM transmitter on the die to adjust a duty cycle of a third output associated with the at least one other RAM transmitter. Other embodiments may be disclosed. |
申请公布号 |
US9049057(B2) |
申请公布日期 |
2015.06.02 |
申请号 |
US201213536567 |
申请日期 |
2012.06.28 |
申请人 |
Intel Corporation |
发明人 |
Krishnamoorthy Satish;Sridharan Harishankar;Trivedi Ritesh B.;Ganapathy Senthilkumar |
分类号 |
G11C7/00;H04L27/00;H04L25/03;G11C7/22 |
主分类号 |
G11C7/00 |
代理机构 |
Schwabe, Williamson & Wyatt, P.C. |
代理人 |
Schwabe, Williamson & Wyatt, P.C. |
主权项 |
1. An apparatus, comprising:
a digital input terminal; a pull-up transmitter coupled to the digital input terminal and configured to selectively delay a rising edge of a first output; a pull-down transmitter coupled to the digital input terminal and configured to selectively delay a falling edge of a second output; and a clock-to-output (TCO) compensation circuit, coupled to the pull-up transmitter, the pull-down transmitter, and at least one random access memory (RAM) transmitter, to compare the first output with the second output and to generate a delay code, based on the comparison, for the at least one RAM transmitter to adjust a duty cycle of a third output associated with the at least one RAM transmitter, wherein to compare the first output with the second output, the TCO compensation circuit includes a rising edge phase detector to compare a delay between rising-edge signals from the pull-up transmitter and the pull-down transmitter. |
地址 |
Santa Clara CA US |