多晶片叠层之封装结构及其封装方法;STACKED MULTI-CHIP PACKAGING STRUCTURE AND MANUFACTURING METHOD THEREOF

摘要

本发明系揭露一种多晶片叠层之封装结构及其封装方法，仅使用一个连接片设置于HS晶片的源极和LS晶片的汲极上实现其电性连接，导电损耗和开关损耗减小，且热耗散效率则得到增强。IC晶片绝缘地连接在连接片上，从而可以叠放到HS晶片及LS晶片所在平面的上方，以有效减少封装后的元件尺寸。本发明中可以将第一载片台、第二载片台的底面暴露在塑封体外；还有多种方法，进一步将连接片上不连接IC晶片的一部分表面暴露在塑封体外；或者在连接片上进一步连接散热板，并使该散热板的一部分表面暴露在塑封体外；或者将散热板插入到塑封体预留的缺口中以接触连接片帮助散热。;A stacked multi-chip packaging structure comprises a lead frame, a first semiconductor chip mounted on the lead frame, a second semiconductor chip flipped-chip mounted on the lead frame, a metal clip mounted on top of the first and second semiconductor chips and a third semiconductor chip stacked on the meal clip; bonding wires electrically connecting electrodes on the third semiconductor chip to the first and second semiconductor chips and the pins of the lead frame; plastic molding encapsulating the lead frame, the chips and the metal clip.