用于降低电晶体阵列中之寄生漏电之技术;REDUCING PARASITIC LEAKAGES IN TRANSISTOR ARRAYS

摘要

一种操作一装置之方法，该装置系包含：一第一导体层，其界定复数个源极导体，其各与一各别群组的电晶体相联结，及复数个汲极导体，其各与一各别电晶体相联结；一半导体层，其界定该等源极与汲极导体之间的半导体通路；一第二导体层，其界定复数个闸极导体，其各与一各别组的电晶体相联结，及一或多个储存电容器导体，其电容性耦合至汲极导体以供一各别组的电晶体用；该方法系包含：使用闸极导体以将电晶体切换于接通与关断状态之间；及使用储存电容器导体以降低一或多个半导体层的导电率(conductivity)，其在接通状态中将各电晶体的汲极导体连接至除了与该电晶体相联结者外的源极及/或汲极导体。; a semiconductor layer defining semiconductor channels between said source and drain conductors; a second conductor layer defining a plurality of gate conductors each associated with a respective set of transistors, and one or more storage capacitor conductors capacitively coupled to the drain conductors for a respective set of transistors; the method comprising: using the gate conductors to switch the transistors between on and off states; and using the storage capacitor conductors to reduce the conductivity of one or more semiconductor layer connecting the drain conductor of each transistor in the on state to source and/or drain conductors other than those associated with that transistor.