METHOD FOR DYNAMICALLY MODIFYING FREQUENCY IN AN ARITHMETIC UNIT BASED ON ONLINE ERROR DETECTION

摘要

The invention relates to a method for dynamically modifying the frequency during the operation of an arithmetic unit within a digital signal processing unit which has adders or multipliers comprised in the critical path. According to the invention, the method consists in dynamically modifying the frequency by the dynamic modification of the clock signal period in an arithmetic circuit (), based on the detection of the errors due to the delays occurred in the circuit, by a detection contention circuit, using a base 7 residual code.