发明名称 PLACEMENT OF MONOLITHIC INTER-TIER VIAS (MIVs) WITHIN MONOLITHIC THREE DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICs) (3DICs) USING CLUSTERING TO INCREASE USABLE WHITESPACE
摘要 Placement of Monolithic Inter-tier Vias (MIVs) within monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) using clustering to increase usable whitespace is disclosed. In one embodiment, a method of placing MIVs in a monolithic 3DIC using clustering is provided. The method comprises determining if any MIV placement clusters are included within a plurality of initial MIV placements of a plurality of MIVs within an initial 3DIC layout plan. The method further comprises aligning each MIV of the plurality of MIVs within each MIV placement cluster in the initial 3DIC layout plan at a final MIV placement for each MIV placement cluster to provide a clustered 3DIC layout plan.
申请公布号 US2015145143(A1) 申请公布日期 2015.05.28
申请号 US201314132098 申请日期 2013.12.18
申请人 QUALCOMM Incorporated 发明人 Samadi Kambiz;Panth Shreepad Amar;Kamal Pratyush;Du Yang
分类号 H01L23/522;G06F17/50 主分类号 H01L23/522
代理机构 代理人
主权项 1. A method of placing Monolithic Inter-tier Vias (MIVs) in a monolithic three dimensional (3D) integrated circuit (IC) (3DIC) using clustering, comprising: determining if any MIV placement clusters are included within a plurality of initial MW placements of a plurality of MIVs within an initial 3DIC layout plan; and aligning each MIV of the plurality of MIVs within each MIV placement cluster in the initial 3DIC layout plan at a final MW placement for each MIV placement cluster to provide a clustered 3DIC layout plan.
地址 San Diego CA US