发明名称 |
ARRAY SUBSTRATE FOR DISPLAY DEVICE |
摘要 |
The present invention provides a display device and a dual gate type thin film transistor (TFT) structure for an electronic device. According to an embodiment, the dual gate TFT structure includes a first gate electrode formed on a substrate; a semiconductor layer formed on the first gate electrode; an insulating layer formed on the semiconductor layer, and including first, second and third contact holes therein; drain and source electrodes in contact with the semiconductor layer respectively through the first and second contact holes; a passivation layer formed on the drain electrode and the source electrode, and including a fourth contact hole therein; a planarization layer formed on the passivation layer, and including a fifth contact hole therein; and a second gate electrode formed on the planarization layer, and in electrical contact with the first gate electrode through the third, fourth and fifth contact holes. |
申请公布号 |
US2015144905(A1) |
申请公布日期 |
2015.05.28 |
申请号 |
US201414475182 |
申请日期 |
2014.09.02 |
申请人 |
LG DISPLAY CO., LTD. |
发明人 |
KIM Jeong-Hwan;CHO Ki-Sul |
分类号 |
H01L29/78;H01L27/12;H01L27/32 |
主分类号 |
H01L29/78 |
代理机构 |
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代理人 |
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主权项 |
1. A display device comprising:
a first gate electrode and a gate insulating layer both formed on a substrate; a semiconductor layer formed on the gate insulating layer; an etch stopper formed on the gate insulating layer, and including first, second and third contact holes therein; a drain electrode and a source electrode both formed on the etch stopper, and both in contact with the semiconductor layer respectively through the first and second contact holes; a first auxiliary pattern in contact with the first gate electrode through the third contact hole; a passivation layer formed on the drain electrode and the source electrode, and including a fourth contact hole therein; a second auxiliary pattern in contact with the first auxiliary pattern through the fourth contact hole; a planarization layer formed on the passivation layer and the second auxiliary pattern, and including a fifth contact hole herein; and a second gate electrode formed on the planarization layer, and in contact with the second auxiliary pattern through the fifth contact hole. |
地址 |
Seoul KR |