发明名称 |
VERTICAL SEMICONDUCTOR DEVICES INCLUDING SUPERLATTICE PUNCH THROUGH STOP LAYER AND RELATED METHODS |
摘要 |
A semiconductor device may include a substrate, and a plurality of fins spaced apart on the substrate. Each of the fins may include a lower semiconductor fin portion extending vertically upward from the substrate, and at least one superlattice punch-through layer on the lower fin portion. The superlattice punch-through layer may include a plurality of stacked groups of layers, with each group of layers of the superlattice punch-through layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Each fin may also include an upper semiconductor fin portion on the at least one superlattice punch-through layer and extending vertically upward therefrom. The semiconductor device may also include source and drain regions at opposing ends of the fins, and a gate overlying the fins. |
申请公布号 |
US2015144877(A1) |
申请公布日期 |
2015.05.28 |
申请号 |
US201414550244 |
申请日期 |
2014.11.21 |
申请人 |
MEARS Technologies, Inc. |
发明人 |
Mears Robert;Takeuchi Hideki;Trautmann Erwin |
分类号 |
H01L27/088;H01L21/324;H01L29/165;H01L29/10;H01L21/8234;H01L29/15 |
主分类号 |
H01L27/088 |
代理机构 |
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代理人 |
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主权项 |
1. A method for making a semiconductor device comprising:
forming a plurality of fins on a substrate by
forming a plurality of spaced apart lower semiconductor fin portions extending vertically upward from the substrate,forming at least one respective superlattice punch-through stop layer on each of the lower fin portions, each superlattice punch-through stop layer including a plurality of stacked groups of layers, each group of layers of the superlattice punch-through stop layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, andforming a respective upper semiconductor fin portion on each of the at least one superlattice punch-through stop layers and extending vertically upward therefrom; forming source and drain regions at opposing ends of the fins; and forming a gate overlying the fins. |
地址 |
Newton MA US |