| 发明名称 |
PHASE CORRECTION OF MULTIPLE PHASE CLOCK TRANSMISSION AND METHOD FOR PERFORMING THE SAME |
| 摘要 |
A circuit includes a first circuit, a second circuit and a third circuit. The first circuit is configured to receive a first phase of a clock signal, a second phase of a clock signal and a first control signal. The first circuit is configured to generate a first interpolated phase of a clock signal. The second circuit is configured to receive a third phase of a clock signal, a fourth phase of a clock signal and a second control signal, and generate a second interpolated phase of a clock signal. The third circuit is configured to receive the first interpolated phase of the clock signal and the second interpolated phase of the clock signal, and generate the first control signal. The first control signal dynamically adjusts the first interpolated phase of the clock signal. |
| 申请公布号 |
US2015145579(A1) |
申请公布日期 |
2015.05.28 |
| 申请号 |
US201314088587 |
申请日期 |
2013.11.25 |
| 申请人 |
TAIWAN SEMICONDUCTOR MANUFACTUING COMPANY, LTD. |
发明人 |
LIN Chih-Chang;CHERN Chan-Hong;HUANG Tsung-Ching;HUANG Ming-Chieh |
| 分类号 |
H03L7/00 |
主分类号 |
H03L7/00 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A circuit comprising:
a first circuit configured to receive a first phase of a clock signal, a second phase of a clock signal and a first control signal, and generate a first interpolated phase of a clock signal; a second circuit configured to receive a third phase of a clock signal, the second phase of the clock signal and a second control signal, and generate a second interpolated phase of a clock signal; and a third circuit configured to receive the first interpolated phase of the clock signal and the second interpolated phase of the clock signal, and generate the first control signal, wherein the first control signal dynamically adjusts the first interpolated phase of the clock signal. |
| 地址 |
Hsinchu TW |
