NOVEL SEMICONDUCTOR PACKAGE WITH THROUGH SILICON VIAS

摘要

The substrate with through silicon plugs (or vias) described above removes the need for conductive bumps. The process flow is very simple and cost efficient. The structures described combines the separate TSV, redistribution layer, and conductive bump structures into a single structure. By combining the separate structures, a low resistance electrical connection with high heat dissipation capability is created. In addition, the substrate with through silicon plugs (or vias, or trenches) also allows multiple chips to be packaged together. A through silicon trench can surround the one or more chips to provide protection against copper diffusing to neighboring devices during manufacturing. In addition, multiple chips with similar or different functions can be integrated on the TSV substrate. Through silicon plugs with different patterns can be used under a semiconductor chip(s) to improve heat dissipation and to resolve manufacturing concerns.

主权项

1. A method, comprising:
forming a plurality of trenches in a first side of a first substrate; filling the trenches with a conductive material; coupling a second substrate to the first substrate through the first side; thinning the first substrate from a second side of the first substrate, the second side being opposite the first side, wherein the thinning is performed until the conductive material filling the trenches is exposed; forming a conductive layer over the second side of the first substrate, wherein the conductive layer is thermal-conductively coupled to the conductive material filling the trenches; and bonding a chip to the conductive layer.