| 发明名称 |
BIT RECOVERY SYSTEM |
| 摘要 |
A particular device includes a resistance-based memory device, a tag random-access memory (RAM), and a bit recovery (BR) memory. The resistance-based memory device is configured to store a data value and error-correcting code (ECC) data associated with the data value. The tag RAM is configured to store information that maps memory addresses of a main memory to wordlines of a cache memory, where the cache memory includes the resistance-based memory device. The BR memory is configured to store additional error correction data associated with the data value, where the BR memory corresponds to a volatile memory device. |
| 申请公布号 |
US2015149864(A1) |
申请公布日期 |
2015.05.28 |
| 申请号 |
US201314088867 |
申请日期 |
2013.11.25 |
| 申请人 |
QUALCOMM Incorporated |
发明人 |
Kim Taehyun;Kim Jung Pill;Kim Sungryul |
| 分类号 |
G06F11/10 |
主分类号 |
G06F11/10 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An apparatus comprising:
a resistance-based memory device configured to store a data value and error-correcting code (ECC) data associated with the data value; a tag random-access memory (RAM) configured to store information that maps memory addresses of a main memory to wordlines of a cache memory, wherein the cache memory comprises the resistance-based memory device; and a bit recovery (BR) memory configured to store additional error correction data associated with the data value, wherein the BR memory corresponds to a volatile memory device. |
| 地址 |
San Diego CA US |
