| 主权项 |
1. A testing backplane apparatus comprising:
a plurality of first test ports, the plurality first test ports configured to receive a first processor assembly, the first processor assembly comprising a target processor assembly under test, the plurality of first test ports comprising one of an even number of first test ports and an odd number of first test ports; a plurality of second test ports, wherein each first test port corresponds to a second test port, the plurality of second test ports connecting to a second processor assembly; and a signal pathway from each first test port to a second test port, the signal pathway comprising a signal path length, the signal path length within a range between a maximum signal path length and a minimum signal path length, wherein each port on the first processor assembly corresponds to each port on the second processor assembly, and wherein the testing backplane apparatus is configured differently from a backplane used as a final destination for operating the first processor assembly. |
