DOUBLE DATA RATE TEST INTERFACE AND ARCHITECTURE

摘要

A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The reduced device test interface is achieved using a double data rate (DDR) signaling technique between the tester and the device. The DDR test interface allows the tester to interface to test circuits within the device, such as IEEE 1500 and/or IEEE 1149.1 test circuits, to provide high test data bandwidth to the test circuits using a minimum of test interface signals. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. Additional features and embodiments of the device test architecture and reduced test interface are also disclosed.

主权项

1. An integrated circuit comprising:
A. cores of functional circuitry for providing the functionality of the integrated circuit; and B. test circuitry coupled to the cores of functional circuitry, the test circuitry including:
i. a separate controller coupled to each core of the functional circuitry, each controller having a controller select input, a control bus input, a data bus input a scan input, and a scan output;ii. selector circuitry coupled to each separate controller, the selector circuitry having a control bus input, a data bus input, select outputs, and a control output, each select output being connected to a select input of a controller;iii. scan router circuitry having a device scan in lead coupled to the scan inputs of the controllers, a device scan out lead selectively coupled to the scan outputs of the controllers, and a control input coupled to the control output of the selector circuitry; andiv. double data rate circuitry, the double data rate circuitry having a double data rate parallel data bus input, a double data rate clock input, a data bus output connected to the data bus inputs of the controllers and the selector circuitry, and a control bus output connected to the control bus inputs of the controllers and the selector circuitry.