SYNCHRONOUS BRIDGE CIRCUITRY AND A METHOD OF TRANSFERRING DATA USING ASYNCHRONOUS BRIDGE CIRCUITRY

摘要

Asynchronous bridge circuitry provides data communication between source circuitry 4 in a source clock domain and destination circuitry 12 in a destinations clock domain. The asynchronous bridge circuitry includes first-in-first-out buffer 20, transmission path circuitry 14, which has an input end coupled to the source circuitry and an output end coupled to the first-in-first-out buffer. The transmission path circuitry has a transmission delay corresponding to a plurality of source clock cycles. Write pointer circuitry 22 located within the source clock domain at the output end 18 of the transmission path circuitry so as to generate a write pointer for the first-in-first-out buffer. Transmission control circuitry 26 located within the source clock domain at the input end 16 of the transmission path circuitry is configured to generate a transmission control signal which controls whether or not the source circuitry is permitted to send data. The transmission control circuitry includes tracking circuitry which stores one or more tracking values for tracking respective state variables of the first-in-first-out buffer and controlling whether or not the transmission control circuitry permits the sending of data from the source to the destination in dependence upon the generated control circuitry.

主权项

1. Asynchronous bridge circuitry for transferring data from source circuitry operating in a source clock domain to destination circuitry operating in a destination clock domain that is asynchronous with respect to said source clock domain, said asynchronous bridge circuitry comprising:
a first-in-first-out buffer located within said source clock domain, said first-in-first-out buffer comprising a buffer output for coupling to said destination circuitry in said destination clock domain and a plurality buffer registers for storing said data values; transmission path circuitry having an input end for coupling to said source circuitry and an output end coupled to said first-in-first-out buffer, said transmission path circuitry configured to transmit said data from said source circuitry to said first-in-first-out buffer with a transmission delay corresponding to one or more source clock signals; write pointer circuitry located within said source clock domain at said output end of said transmission path circuitry and configured to generate a write pointer coupled to said first-in-first-out buffer to select a current write location within said first-in-first-out buffer and corresponding to one of said plurality of buffer registers; and transmission control circuitry located within said source clock domain at said input end of said transmission path circuitry and configured to generate a transmission control signal for controlling whether or not said source circuitry is permitted to send said data to said first-in-first-out buffer, wherein said transmission control circuitry comprises tracking circuitry configured to store one or more tracking values for tracking respective state variables of said first-in-first-out buffer, said transmission control circuitry generating said transmission control signal in dependence upon said one or more tracking values.